This invention relates generally to processing within a computing environment, and more particularly to a target memory hierarchy specification in a multi-core computer processing system.
Prefetch instructions enable a processor to speculatively implement a memory access for a cache line, whereby the cache line is brought into a cache before it is requested by the processor. In this manner, prefetching provides a way to minimize latencies associated with accessing memory by moving the needed data to a closer location in the memory hierarchy before it is needed.
Traditionally, prefetch instructions are issued only by the processor that will consume the prefetched data. Therefore, the location in the memory hierarchy to which the data should be prefetched is assumed to have affinity with the processor from which the prefetch instruction is issued. In a multi-core processing environment, a prefetch instruction issued by one of the cores will load the prefetched data into the cache of the requesting core; however, in some instances a prefetch request for data needed by one of the cores may be initiated by another core. In these situations the efficiency of the prefetch command is reduced because the data is stored in the local cache of the requesting core rather than the local cache of the core that needs the data.